Method and arrangement for transmitting digital signals

ABSTRACT

During the transmission of digital signals which are interlaced in a multiplex signal, plesiochronic clock frequencies are also matched by means of positive-zero-negative stuffing. In this case, the time intervals of the phase changes can be large in comparison with the time constant of a phase low-pass filter which is formed by a phase-locked loop at the receiving end, which results in a jitter of approximately 1 UI. This jitter can be reduced if additional stuffing processes are inserted in pairs, in such a manner that an additional positive stuffing process (PST) is followed by such a negative stuffing process (NST) or, overall, vice versa, and if the time intervals within the pairs and/or between the pairs are selected in such a manner that the mean value of the phase difference between an incoming digital signal at the transmission end and an outgoing digital signal at the transmission end, which is contained in the multiplex signal, averaged over a specific time duration, remains approximately constant.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a method and apparatus fortransmitting at least one incoming digital signal in a data channelhaving a constant clock rate, in the case of which the data rates arematched by positive-zero-negative stuffing in that, on reaching an upperdecision threshold and a lower decision threshold of the phaseseparation, additional stuffing processes are produced, beyond therequired stuffing processes.

2. Description of the Related Art

The positive, the negative and the positive-zero-negative stuffingtechniques are described in Section 1.4, pages 8 to 12 and 15 to 20, May1983 issue and pages 13 to 14, May 1984 issue, of the loose-leafdocument "Digitale Ubertragungstechnik" [Digital transmissiontechnology], Kahl, R. v. Becker's Press, G. Schenck, Heidelberg.

In order to be able to transmit transmitted data signals in a datachannel having a constant bit rate, the transmission bit rate must bematched to the bit rate of the digital signal. For this purpose, thetransmitted data signal contains stuffing points at periodic intervals,which stuffing points contain bits of the digital signal or dummy bits,as required.

If the stuffing point is planned to contain data bits of the digitalsignal and dummy bits to the extent by which the bit rate of the digitalsignal lags behind that of the transmission bit rate reserved, theinsertion of the dummy bits into the stuffing points is designatedpositive stuffing.

If the stuffing point is planned to contain dummy bits and data bits ofthe digital signal to the extent by which the bit rate of the digitalsignal exceeds that of the transmission bit rate reserved, the insertionof the data bits into the stuffing points is designated negativestuffing.

Stuffing methods which use both types of stuffing are designatedpositive-zero-negative stuffing methods.

These methods are used even when multiplex signals on a lowerhierarchical level are to be combined to form a common multiplex signalon a higher hierarchical level.

Each stuffing process having a bit produces a phase change of theoutgoing (transmitted) digital signal by one UI (unit interval).Positive stuffing causes the phase to lag by one UI with respect to theincoming digital signal; negative stuffing causes a phase lead of oneUI. The phase changes are smoothed by means of a phase-locked loop PLLat the destination (for example during recovery of the transmittedsignal from the multiplex signal). On the basis of its dimensioning, thephase-locked loop acts like a low-pass filter having a cutoff frequencyf₀. The time constant of the low-pass filter is T=1/(2*π*f₀). Theamplitude of the phase changes (jitter) caused by stuffing is greatlyreduced by the phase-locked loop if the time interval between the phasechanges is very small in comparison with the time constant T, that is tosay if the frequency with which the stuffing processes occur is veryhigh in comparison with the cutoff frequency f₀.

In the case of the positive-zero-negative stuffing method, the timeintervals between the phase changes can be large in comparison with thetime constant T. In this case, the amplitudes of the phase changes arenot damped much by the phase-locked loop and the values of the jitterare virtually one UI.

From the publication "Jitter Analysis of Asynchronous Payload Mappings",T1X1.4/86-447, Contribution to T1 Standards Project-T1X1.4, 12.11.86,pages 9 and 10, "threshold modulation" is furthermore known, in the caseof which thresholds of the phase difference between an incoming digitalsignal at the transmission end and an outgoing digital signal at thetransmission end are varied, so that additional stuffing processes areproduced. In this case, the jitter assumes a higher frequency which canbe filtered more easily.

The European Patent Specification 0 248 551 A2 describes a method forsynchronization of asynchronous data (stuffing method) which leads to anincrease in the stuffing frequency and hence in the jitter frequency.The use of stepped characteristics for the threshold values forinitiating the additional stuffing processes is also known from thisdocument. In the case of this method, the superfluous stuffing processesare disadvantageous when the (synchronous) signal which is to betransmitted has the desired phase. The arrangement is likewise dependenton considerable circuit complexity.

The European Patent Application 0,192,492 likewise describes a methodfor increasing the stuffing frequency in the case of apositive-zero-negative stuffing method.

SUMMARY OF THE INVENTION

The invention is based on the problem of further reducing the jittervalues in the case of the positive-zero-negative stuffing, and providesfor transmitting at least one incoming digital signal in a data channelhaving a constant clock rate, whereby the data rates are matched bypositive-zero-negative stuffing in that, on reaching an upper decisionthreshold and a lower decision threshold of the phase separation,additional stuffing processes are produced, beyond the required stuffingprocesses. The invention is particularly characterized by stuffingprocesses being additionally carried out in pairs such that anadditional positive stuffing process is followed by a negative stuffingprocess, or vice versa, the time intervals in each case between apositive stuffing process and a negative stuffing process being variedwith respect to the intervals in each case between the negative and thesubsequent positive stuffing process, as a function of the phaseseparation, in such a manner that the mean value of the phase separationof the outgoing digital signal from the incoming digital, formed betweensuccessive stuffing processes of the same direction, is approximatelyconstant, the mean value of the phase separation between the outgoingdigital signal and the incoming digital signal correspondingapproximately to the rated value of the phase separation of zero, as aresult of the additional stuffing processes, a stuffing superframe,which is defined between two stuffing processes in the same direction,having a constant number of pulse frames and the position of theintervening stuffing process in the other direction is varied inaccordance with the phase separation, an upper decision threshold, forinitiating the one stuffing process and having a step-shaped coursebeing reduced step-shaped in a stuffing superframe from a maximum valuewhich is less than or equal to one unit interval to a minimum value of ≧zero, and is then set to the maximum value again at the beginning of thenext stuffing superframe, a lower decision threshold for triggering theother stuffing process proceeding in the same direction at the spacingof one unit interval, and the maximum value of the lower decisionthreshold being less than the minimum value of the upper decisionthreshold, and the stuffing superframe and the decision thresholds,which run in a stepped manner, being selected in such a manner that,during one period duration of the stuffing superframe, the phase of theoutgoing digital signal changes with respect to the incoming digitalsignal by less than the difference between two adjacent decisionthreshold values.

An advantageous arrangement for carrying out the method includes meansfor transmitting at least one incoming digital signal via a data channelhaving a constant clock rate, whereby the data rates are matched bypositive-zero-negative stuffing in that, on reaching a predeterminedupper or lower phase separation, additional stuffing processes areproduced, beyond the required stuffing processes, having a memory intowhich the incoming digital signal is written using a write clock andfrom which reading out takes place using a read clock, having a systemcontroller for controlling the outgoing digital signal and the stuffingprocesses, and having a threshold value decision device which initiatesa stuffing process in the event of an upper stepped decision thresholdbeing exceeded or a lower decision threshold being undershot, thethreshold value decision device having an upper decision threshold forthe phase separation of less than one unit interval and ≧0, which runsin a stepped manner and changes with each of N pulse frames of astuffing superframe, and has a lower decision threshold, which proceedsuniformly therewith, in that phase deviations of less than one unitinterval are determined which initiate a stuffing process when adecision threshold is upwardly or downwardly transgressed, in that thesystem controller has a frame generator which forms the pulse frame andcontrols a frame number counter, in that a control logic circuit isprovided as the threshold decision device, to which control logiccircuit time criteria are passed from the frame generator and from theframe number counter, and in that the control logic circuit produces acontrol signal which corresponds to a pulse, which is allocated to eachand every pulse frame of a stuffing superframe, at different testingtimes, which pulse stores a difference value which indicates theoccupancy level of the memory.

The advantage which is achieved using the invention is that the meanvalue of the phase of the transmitted digital signal fluctuates less, asa result of which the jitter is considerably reduced.

The arrangement as disclosed herein can be implemented with littleadditional complexity.

Refinements of the method further include difference values whichindicate the occupancy level of a stuffing memory being evaluated asdecision thresholds for initiating additional stuffing processes inpairs, and the difference values being evaluated at different testingtimes, of which in each case one is allocated to one of the pulse framesof a stuffing superframe. Preferably, at the transmission end, aplurality of outgoing digital signals is combined to form a multiplexsignal, and, at the receiving end, the multiplex signal is split intothe individual signals which are read out using a read clock at thereceiving end, which is obtained in a phase-locked loop.

BRIEF DESCRIPTION OF THE DRAWINGS

Exemplary embodiments of the invention are described in more detail inthe following text, with reference to figures, in which:

FIG. 1 shows a known response of the phase deviation of a digital signalto be transmitted, with respect to the desired value of the phase, overa large number of frames, in the case of the knownpositive-zero-negative stuffing,

FIG. 2 shows a response of the phase deviation of a digital signal to betransmitted, normalized with respect to the desired value of the phase,over a number of the stuffing decision times, in the case of the methodaccording to the invention, and

FIG. 3 shows a response of the phase deviation using other decisionthresholds,

FIG. 4 shows a response of the phase deviation of the transmitteddigital signal, with respect to the desired value of the phase, over thenumber of frames in FIG. 1, using the method in FIG. 2.

FIG. 5 shows a pulse frame,

FIG. 6 shows an arrangement for carrying out the method,

FIG. 7 shows a timing diagram for address control,

FIG. 8 shows a timing diagram for determining the phase difference,

FIGS. 9, 10 show further timing diagrams for this purpose,

FIG. 11 shows the principle of a system controller and

FIG. 12 shows a receiving section.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows the response of the phase deviation PA in UI (unitintervals) of the outgoing (transmitted) digital signal DSa at thetransmission end--more precisely its "desired value" of the phase--withrespect to the incoming digital signal DSe at the transmission end, andthe matching of the outgoing digital signal DSa to the data rate of theincoming signal, using stuffing processes. From the arrangement shown inFIG. 6, it can be seen that the incoming digital signal DSe is initiallywritten into a memory 2. It is read out of this memory as the outgoingdigital signal DSa and is transmitted (as a rule) at a slightlydeviating data rate (corresponding to the nominal transmission capacityof the data channel).

The deviations from the data rate of the incoming digital signal arecompensated for by stuffing. At this stage, it is not intended here togo into the fact that the outgoing digital signal DSa is called up by agapped clock. This is intended to take into account the term "desiredvalue of the phase". As an example of this: if the data rates of thedigital signal which is transmitted (outgoing) without stuffing and ofthe incoming digital signal are identical, then there is no phasedifference between the digital signals in the representation in FIG. 1.A circuit-dependent constant phase difference is not taken into account.A constant upper decision threshold ESo at +0.5 UI and a lower decisionthreshold ESu at--0.5 UI are defined.

In the example, the stuffing rate is assumed to be 0.01, that is to saythe phase deviation PA has changed by 1 UI after every hundred pulseframes, so that a stuffing process takes place.

In consequence, in this example--if the data rate of the transmitteddigital signal is greater than that of the incoming signal--the phasedeviation PA likewise increases by 0.01 UI per pulse frame. Afterexceeding the upper decision threshold ESo at +0.5 UI, positive stuffing(PST) is carried out, as a result of which the phase deviation PAchanges by 1 UI to a value of approximately--0.5 UI. Subsequently, itincreases uniformly again by 0.01 UI per pulse frame R. The decisionthreshold +0.5 UI is reached again after 100 pulse frames R and afurther stuffing process PST is initiated. This results in a slow jitter(phase fluctuations) which can be damped only inadequately by a phaselow-pass filter at the receiving end, which filter is formed by thephase-locked loop (PLL) of a desynchronizer.

In the case of the known solution, the phase-locked loop has--as afunction of the deviation between the data rate and transmissionrate--to process a full phase change of one UI at large intervals.

In the case of the invention, phase changes are produced morefrequently, as is shown in FIG. 4, and the low-pass effect of thephase-locked loop at the receiving end is utilized. Negative andpositive phase changes are transmitted alternately, that is to saypositive and negative stuffing are carried out alternately. These pairsof stuffing processes PST and NST which, however, at the transmissionend produce no resultant phase correction whatsoever between theincoming digital signal and outgoing digital signal, are continued untila specific phase deviation is exceeded, which leads to a "real"individual stuffing process. The interval between the "real" stuffingprocesses is, as before, dependent on the difference between the bitrate of the incoming digital signal and the transmission bit rate of thedata channel which is used.

In spectral terms, the method has the effect that, at the receiving end,the spectrum of the control voltage produced by the stuffing processeshas higher frequencies which are filtered out by the phase-locked loop,so that jitter is largely prevented.

The principles for initiating the additional stuffing processes in pairsare intended to be explained with reference to FIG. 2. This figure onceagain shows a response of the phase deviation PA of an outgoing(transmitted) digital signal DSa, shown normalized with respect to theincoming digital signal DSe over the stuffing decision times STE ofsuccessive pulse frames R. The decision characteristics for an upperdecision threshold ESo and for a lower decision threshold ESu are shownby thick lines, the two decision threshold values ESo1, ESo2, . . . ,and ESu1, ESu2, . . . , respectively of which decision thresholds changein a stepped manner in steps of 0.2 UI in the same direction, theinterval between two decision thresholds ESo and ESu which areassociated in time always being 1 UI. A stuffing superframe SUR in thiscase comprises N=5 pulse frames to which in each case five differentupper and lower decision threshold values are allocated. If, at the timeof a stuffing decision STE, a phase difference PA is above the upperdecision threshold ESo (or at least reaches said threshold), it ispositively stuffed; this is designated by PST once again.

If, on the other hand, the phase difference PA is below the lowerdecision threshold ESu, it is negatively stuffed, designated by NST. Thephase difference PA changes by 1 UI as a consequence of each stuffingprocess.

The continuous thin line shows an optimum phase difference PA of 0, inthe case of which no stuffing is required. This is the desired phase.The dashed-dotted line and the dashed line in contrast show two phases,in the case of which stuffing is carried out in pairs in each case. Themean value--averaged over the period duration of the stepped decisioncharacteristic, that is to say of a stuffing superframe--is, however,always approximately zero.

FIG. 2 shows that the duration between the successive stuffing processesNST and PST (or PST and NST) depends on the phase deviation. If PA=0 orif none of the decision thresholds is exceeded, then no stuffingprocesses take place.

If PA is positive and large (dashed-dotted line), then negative stuffingand positive stuffing follow in successive pulse frames R.

If PA is negative and large (dashed lines), the interval betweennegative stuffing and positive stuffing is, in contrast, large.

Mean phase deviations PA result in mean intervals. The dashed line andthe dashed-dotted line run exactly horizontally only when notime-dependent phase changes (for example in accordance with FIG. 1)take place. The mean value of the phase deviation is alwaysapproximately zero.

FIG. 3 shows a variant of the decision characteristics, which form thebasis of the phase response shown in FIG. 4. The separations of thedecision characteristics from the zero line are not equal. The maximumdecision threshold ESo is identical to the threshold for the positivestuffing processes, which are not in pairs, so that, in the event ofpositive phase deviations, only three additional decision thresholdsinitiate stuffing processes in pairs. In the case of a stuffing rate of0.01, which is unchanged from FIG. 1, the upper decision threshold ESois varied in such a manner that the decision threshold values assume thevalues 1 UI, 0.75 UI, 0.5 UI, and 0.25 UI in N=4 successive frames R, atwhich point the decision threshold changes to 1 UI again. The lowerdecision threshold ESu runs parallel thereto with values which are lowerby 1 UI. This is repeated after the stuffing superframe period SUR,which covers four frames R.

FIG. 4 shows a response of the phase deviation of the outgoing digitalsignal DSa (desired values of the phase) with respect to the incomingdigital signal DSe. In the example of the superimposition in FIG. 1, therepresentation here corresponds to the additional stuffing processeswhich are initiated in accordance with FIG. 3.

The above numbers were selected so that the effect according to theinvention can be identified as clearly as possible. After 25 frames R,when the phase difference reaches 0.25 UI, positive stuffing andsubsequent negative stuffing in pairs are instituted in such a mannerthat the mean value of the phase deviation PA after one stuffingsuperframe is zero. It then rises in accordance with the actual phasedeviation. In FIG. 4, the mean value line ML was shown by dashed lines.A mean value line which is symmetrical with respect to the zero line canalso be achieved by a modified arrangement of the decision thresholds.This does not result in a further reduction of the jitter.

The interval between positive stuffing PST and negative stuffing NST,which is initially only one frame R, is increased with an increasingphase difference in the case of a greater number of frames R. The meanvalue line is once again correspondingly shifted with respect to thezero line after 50 and 75 frames, with a change in the intervals betweenthe stuffing processes. At approximately the hundredth frame, when thephase deviation PA briefly reaches approximately 1 UI, the associatednegative NST after a positive stuffing process PST is omitted, and thephase difference falls to zero.

At approximately the 125th pulse frame, a further positive stuffingprocess PST once again takes place, which is followed immediately by anegative stuffing process NST again, and the described process isrepeated.

The lowest decision threshold value, up to which point no stuffingprocesses take place, can be selected to be as small as desired.

It is also clear from FIG. 4 that a staircase curve having a pluralityof steps (a sawtooth in the ideal case) leads to smaller deviations fromthe desired value PA=0 of the phase difference. In consequence, thefrequency with which the stuffing processes occur is, of course, reducedcorresponding to the increase in the decision thresholds.

It is intended to explain the method of operation of the invention inmore detail before going into details of the arrangement.

An outline circuit diagram of the receiving section is shown in FIG. 12.It contains a memory 13 and a phase-locked loop 14 having avoltage-controlled oscillator (VCO), a phase-comparison circuit 16 and alow-pass filter 17. The read clock TRE and write clock TWE at thereceiving end are each passed via a frequency divider 18 or 19respectively, to the phase-comparison circuit 16.

The data bits, which arrive irregularly as a result of stuffingprocesses, of the digital signal are converted by the phase-locked loopinto a digital signal DSe which has a data rate that is as constant aspossible and corresponds as far as possible to the incoming digitalsignal DSe at the transmission end. In the case of multiplex systems,the received multiplex signal MS is initially split, by means of ademultiplexer 20, into a plurality of digital signals.

At the receiving end, the phase difference of the transmitted digitalsignal from the digital signal DSe and a read clock TRE at the receivingend largely corresponds to the response shown in FIG. 4. When consideredwith respect to time, the transmission of the stuffing processes has thefollowing meaning for the phase-locked loop at the receiving end: Thestuffing processes on each occasion cause the reception of oneinformation bit less or one information bit more, and hence one clockpulse of the associated write clock TWE more or less and hence, at theoutput of a frequency divider which is connected upstream of thephase-locked loop, on each occasion a positive or a negative phasechange in the reference variable, that is to say the control voltage(control deviation) for the oscillator of the phase-locked loop. Theadditional positive stuffing processes and the negative stuffingprocesses occur during one sawtooth period (FIG. 4) in the initial,central and final region for different time and, as a result of thelow-pass filtering effect, cause the mean oscillator frequency to havesmaller phase fluctuations. In other words: the phase-locked loop iscontrolled even before the "real" stuffing process takes place.

The method of operation of the method can also be explained in such amanner that, at the receiving end, as a result of the stuffing processeswhich are frequently carried out, the resulting large phase differenceare eliminated by the low pass filtering effect of the phase-locked loopand, as a result of the different stuffing intervals, the mean phasedeviation (pulse-width modulation) fluctuates less. The time constant Tof the phase-locked loop should be greater than the duration of onestuffing superframe.

FIG. 5 shows a simplified pulse frame Rk. The latter contains a frametag RKW, service bits SB, useful information NI, stuffing information STand two time slots B for the transmission of stuffing bits orinformation bits. The stuffing information ST indicates whether stuffingbits or information bits are intended to be transmitted in the timeslots B. These bit positions are designated by PST and NST. The frameposition RP indicates the time slots for in each case one bit in thepulse frame. The decision time EST in this case occurs at the start oftransmission of the useful information. It is, of course, also possibleto stuffing using a plurality of bits. In addition, FIG. 5 shows a writeclock TW and a read clock TR, which will be described later.

In multiplex systems, a plurality of digital signals are combined toform a multiplex signal which is transmitted inserted in a pulseframe/pulse superframe. The structures specified in accordance withG.709 in the CCITT Recommendations, for example, are also used as thepulse frame and pulse superframe. Likewise, digital signals can also beinserted into pulse frames which are used purely internally, for examplein switching systems or cross-connectors.

FIG. 6 shows a multiplexing arrangement at the transmission end. Saidarrangement consists of a memory 2 whose addresses are determined by twoaddress counters 1 and 3. The digital signal DSe is written into thememory 2. The memory output is connected to a multiplexing device 4. Thecounter outputs supply the write address AW and the read address AR.Both are supplied to a subtraction circuit 5 which, at its output, emitsa difference value DW which is stuffing-stored in a latch 6. Its outputis connected to a threshold value decision device 7 which, in the eventof the decision threshold values being exceeded or undershot, suppliessignals SPS and SNS, for positive stuffing and negative stuffingrespectively, to a system controller 8 (frame control).

The system controller operates using the multiplexing clock TM. Itsobject is to combine a plurality of digital signals DS to give amultiplex signal MS, to merge in additional information items such asframe tag words, service bits etc. and to control the stuffingprocesses. In terms of circuitry, these devices are known to any personskilled in the art of multiplexing technology. The digital signal DSe iswritten into the memory 2 using a common write clock TW. Reading-outtakes place using a somewhat faster gapped clock, the read clock TR,which, however, has the same number of pulses per pulse frame. Theoccupancy level of the memory 2 controls the stuffing processes. Thedifference between the write address AW and the read address AR isformed for this purpose. If the difference value DW exceeds an upperthreshold value, the difference value DWo, then negative stuffing takesplace, in that a further data bit is read out of the memory 2 and isinserted in the region B of the pulse frame. If the difference value isless than the lower difference value DWu, then positive stuffing takesplace.

Up to this point, this arrangement corresponds to the method ofoperation of the known arrangement. It should be noted as a precautionthat the upper difference value DWo corresponds to the lower decisionthreshold ESu in FIGS. 1 to 4, and the lower difference value DWucorresponds to the decision threshold ESo.

One decision time EST is initially defined in a known manner in eachpulse frame in order to determine the difference value. The differencevalue DW is evaluated at the decision time EST (FIG. 5). A reading pulsecan now be extracted towards the end of the pulse sequence of the readclock TR in the case of a positive stuffing process, or, in the case ofa negative stuffing process NST, a further information bit can be calledup from the memory 2, by means of an additional read pulse. The methodcan also be used by changing the mean transmission rate of a bit whichis inserted, for example, into each second pulse frame, without phasedeviations (desired stuffing rate 0.5).

FIG. 7 shows a timing diagram to illustrate the operation forcontrolling the stuffing process. The addressing of the memory 2 via theaddress counters 1 and 3 in each case takes place by means of amodulus-M addition, corresponding to the number M of information bits ina pulse frame. The changes in the write address AW and the read addressAR are shown in FIG. 7. Using the write clock TW and the read clock TRrespectively, the write address AW and the read address AR are in eachcase increased by the value "1" in order to drop back to 0 when thecounter state is M-1. During the transmission of the additionalinformation, no useful information is called up from the memory 2, thatis to say the read address AR remains constant. If the clock frequenciesof the incoming digital signal DSe and of the outgoing digital signalDSa correspond, in terms of their desired clock frequencies, and thedata rates of the outgoing digital signal (without stuffing) and of theincoming digital signal correspond then the timing diagram shown in FIG.7 is repeated periodically with the following pulse frame R (k+1) etc.However, if the clock frequencies deviate from the desired frequencies,then positive or negative stuffing is required. During positivestuffing, a dummy bit is inserted into the pulse frame (or the pulsesuperframe) of the outgoing digital signal DSa, instead of aninformation bit, that is to say a read pulse is suppressed, as a resultof which the read address AR initially remains constant. This is shownby the dotted line in FIG. 7. On the other hand, during negativestuffing, an additional information bit is read out of the memory 2 andis inserted into the pulse frame in the time slot B of the outgoingdigital system. This is shown by the dashed line in FIG. 7.

Initially, a stuffing process is initiated whenever the differencebetween the write address AW and the read address AR exceeds the upperdifference value DWo or is less than the lower difference value DWu. Asalready mentioned, it is now intended to determine even smaller phasedifferences between the outgoing digital signal and the incoming digitalsignal and the desired positions of the write clock and the read clockin order to be able to initiate stuffing processes additionally inpairs. One possibility for determining the phase deviation is to measurethe phase difference between the write clock and read clock directly, itbeing necessary to take into account the desired positions in the caseof a read clock which has gaps.

An advantageous development of this method uses a plurality of testingtimes PP1 to PP4 corresponding to the number of pulse frames R in astuffing superframe SUR, instead of a single decision time EST.

From FIG. 5 it can be seen that the period duration of the gapped readclock TR is shorter than that of the common write clock TW. This resultsin the response, shown in FIG. 8, of the read clock, of the write clockand of the difference value DW--that is the difference between the bitswhich are read in and those which are read out, and the occupancy levelof the memory. If the write clock, which is likewise shown, and the readclock correspond in terms of their desired frequencies, and the datarates of the outgoing digital signal (without stuffing) and of theincoming digital signal correspond, the timing diagram which is shown inFIG. 8 is likewise repeated periodically using each pulse frame.

This representation corresponds to the phase deviation PA=0, in the caseof which the phase of the outgoing digital signal corresponds exactly toits "desired value" (description of FIG. 1). If the evaluation of thedifference values takes place at one of the testing times PP1 to PP4,which replace the conventional stuffing decision time STE, then neitherthe upper difference value DWo=16 nor the lower difference value DWu=14is reached.

Instead of an "amplitude threshold value" ESo, ESu for the phasedeviation, the process is now based on the following: the phasedifference PN1 (FIG. 8) between the effective edges of the read clock TRand of the write clock TW and the first testing time PP1 corresponds, inthe case of the desired position, to the difference in the periodduration of the write clock TW and of the read clock TR. The phasedifference PN1 is evaluated when the phase of the write clock TW isshifted forwards in comparison with that of the read clock TR. Doublethe phase difference PN2 results for the subsequent testing time PP2. Amultiple of this phase difference PN1 can thus be determined by suitableselection of the testing time. In the event of phase shifts in theopposite direction, the phase differences between the effective edge ofthe read clock and the preceding effective edge of the write clockapply. Only the phase difference PP1 of this is shown in FIG. 8.

When the write and read clocks deviate from their desired frequencies,the phase differences PN and PP deviate from their "desired phasedifferences" which are shown in FIG. 8, corresponding to the phasedifference PA.

A deviation which leads to shifts in the clocks, which shifts aregreater than the phase differences shown in FIG. 8, is evaluated in acorresponding manner to a decision threshold being exceeded, and causesa stuffing process. The phase difference PN1 corresponds to the stepheight of the decision characteristics shown. The phase difference, andhence the phase difference, are determined via the occupancy level ofthe memory.

In contrast to the examples shown in FIG. 1 to FIG. 4, in FIG. 9 it hasnow been assumed that the phase of the write clock is moving forwards intime (to the left of the drawing) relative to the read clock. The writeclock thus has a higher frequency than the read clock (or the desiredvalue).

As a consequence of the phase shift, a change in the sequence betweenthe change in the read address and the write address at the time of thetesting time PP1 takes place between the clocks, that is to say thewrite clock has "overtaken" the read clock. At the testing time PP1, thedifference value reaches the upper difference value DWo=16 and thusinitiates a stuffing process. Since the upper difference value (theincoming digital signal has a higher data rate than the outgoing digitalsignal) has been reached here, it is negatively stuffed. In consequence,the difference value is reduced by 1 at the end of the pulse frame. FIG.10 applies to the subsequent pulse frame. The stuffing decision nowtakes place one pulse frame R and additionally one period of the readclock later at the next testing time PP2. There, the difference valueDW=14, the lower difference value DWu=14 is reached, and it ispositively stuffed. The testing time is changed from pulse frame topulse frame corresponding to the number of pulse frame periods in astuffing superframe until the process starts again with the firsttesting time PP, of the testing time which follow directly thereon.Further timing diagrams for the subsequent stuffing processes aredispensed with here.

Thus, the difference between the write clock and the read clock is nolonger measured at a specific testing time in the case of this process,the determination of whether the sequence of changing the write addressand the read address has shifted being carried out at different testingtimes, instead. An evaluation of the difference value at the testingtimes is sufficient for this purpose.

Occasionally a change in the difference value Dw occurs, which initiatesa stuffing process. The testing times can be defined within the pulseframe corresponding to the desired differences between the decisionthresholds. In the present example, four periods of the write clockcorrespond to five periods of the read clock. The change between thewrite address and read address at the testing time PP1 corresponds tothe phase shift by a quarter of one period of the read clock and a fifthof one period of the write clock within a pulse frame.

FIG. 11 shows the system controller 8 in detail. It contains a framegenerator 9 which defines the pulse frame via its frame counter. Theframe counter controls a frame number counter 10 which defines thenumber of pulse frames per stuffing superframe and additionallydetermines the decision thresholds corresponding to the present frame Rof a stuffing superframe in order to initiate stuffing processes--thatis to say the decision characteristic. The outputs of the framegenerator 9 and of the frame number counter 10 are connected to acontrol logic circuit 11 to which control signals SNS and SPS aresupplied from the threshold value decision device 7. Specific timeconditions are determined and, in addition, the control signals havingtime conditions are linked to one another by means of a combinationallogic circuit, in the control logic circuit. A control signal STP todetermine the testing times PP1 to PP4 is output, in that a clock pulseis emitted at the corresponding time in each pulse frame. In addition, afurther read control signal SR is produced which, via a logic gate 12,produces the gapped read clock TR from a read clock signal TRSand--controlled by the stuffing signals SNS and SPS--inserts or extractsindividual pulses of the read clock during stuffing processes. Althoughother modifications and changes may be suggested by those skilled in theart, it is the intention of the inventor to embody within the patentwarranted hereon all changes and modifications as reasonably andproperly come within the scope of his contribution to the art.

I claim:
 1. An arrangement for transmitting at least one incomingdigital signal via a data channel having a constant clock rate, wherebydata rates of a matching step are matched by positive-zero-negativestuffing in that, on reaching a predetermined upper or lower phaseseparation, additional stuffing processes are produced, comprising:amemory into which an incoming digital signal is written using a writeclock and from which reading out takes place using a read clock, asystem controller connected to said memory for controlling an outgoingdigital signal and the stuffing processes, and a threshold valuedecision device which initiates a stuffing process in the event of anupper stepped decision threshold being exceeded or a lower decisionthreshold being undershot, said threshold value decision device havingan upper decision threshold for a phase separation of less than one unitinterval and ≧0, which runs in a stepped manner and changes with each ofN pulse frames of a stuffing superframe, and having a lower decisionthreshold, which proceeds uniformly therewith, means for determiningphase deviations of less than one unit interval which initiate astuffing process when a decision threshold is upwardly or downwardlytransgressed, said system controller including:a frame generator whichforms the pulse frame; a frame number counter connected to an output ofsaid frame generator to count the pulse frames; and, a control logiccircuit connected to receive control logic circuit time criteria fromthe frame generator and from the frame number counter, and the controllogic circuit produces a control signal which corresponds to a pulse,which is allocated to each and every pulse frame of a stuffingsuperframe, at different testing times, which pulse stores a differencevalue which indicates the occupancy level of the memory.
 2. A method fortransmitting at least one incoming digital signal in a data channelhaving a constant clock rate, comprising the steps of:storing theincoming digital signal in a buffer memory; matching a data rate of theincoming digital signal to the constant clock rate of the data channelby positive-zero-negative stuffing wherein a stuffing process isinitiated if a phase difference between the incoming digital signal andan outgoing digital signal from said storing step reaches a decisionthreshold level, said decision threshold being one of an upper decisionthreshold and a lower decision threshold; having a stuffing superframewhich is defined between two possible stuffing processes in a samedirection between successive of said positive and negative stuffingprocesses, having a constant number of pulse frames; using foradditional stuffing processes beyond required stuffing processes,wherein said required stuffing processes are implemented when the phasedifference exceeds one unit interval, further comprises the steps of:theupper decision threshold which runs in a stepped manner from a maximumvalue which is not more than one unit interval to a minimum value of notless than zero for initiating the stuffing process and the lowerdecision threshold which runs in a same manner from a maximum valuewhich is less than the minimum value of the upper decision threshold ata spacing of one unit interval for initiating an opposite other stuffingprocess; reducing the decision thresholds during each period duration ofthe stuffing superframe step-by-step with each frame from the maximumvalues to the minimum values corresponding to said upper and lowerdecision thresholds and then setting the decision thresholds to themaximum values again at a beginning of a next superframe; carrying outthe additional stuffing processes in pairs by using smaller decisionthresholds of said reducing step such that an additional positivestuffing process is followed by a negative stuffing process or such thatan additional negative stuffing process is followed by a positivestuffing process; varying time intervals during said carrying out stepbetween said positive stuffing process and said negative stuffingprocess and between said negative stuffing process and a subsequentpositive stuffing process as a function of the phase difference and thedecision thresholds and as a result of the additional stuffing processesa mean value of the phase difference between the outgoing digital signaland the incoming digital signal is approximately constant and reachesapproximately a rated value of zero; evaluating difference values whichindicate an occupancy level of a buffer memory as said decisionthresholds for initiating the additional stuffing processes at differenttest moments, each test moment being allocated to one of the pulseframes of a stuffing superframe and one period of the pulse frames andan additional small time difference from a last test moment aparttransmitting the outgoing digital signal having a rate adjusted bystuffing.
 3. A method as claimed in claim 2, further comprising thesteps of:combining, at a transmission end, a plurality of outgoingdigital signals including said stuffing signals corresponding to saidpositive, zero, or negative stuffing signals to form a multiplex signal,and splitting, at a receiving end, the multiplex signal into individualsignals which are read out using a read clock at the receiving end,which is obtained in a phase-locked loop.
 4. A method as claimed inclaim 2, further comprising the step of:selecting the stuffingsuperframe and the decision thresholds in such a manner that the phasedifference between the outgoing digital signal and the incoming digitalsignal changes during the stuffing superframe less the differencebetween two adjacent decision threshold values.